Chip/Package Co-Design Might Fulfill a 2nd “Moore’s Law”
Gordon Moore forecasted the death of Moore’s legislation and imagined in its area bigger systems developed from smaller sized, individually packaged, adjoined systems, according to Anna Fontanelli, Monozukuri S.p.A. CEO and Creator.
Opening her discussion the other day on ingenious advanced product packaging techniques throughout the IEEE EDAPS 2023 Crossbreed Seminar, at the Sugar Coastline Hotel, Wolmar, Flic-en-Flac, Republic of Mauritius, Ms. Fontanelli stated that the semiconductor visionary properly forecasted stacked-die advanced product packaging modern technology as the development follower to his very own Moore’s legislation. She utilized Moore’s long-range vision to specify the Advanced Product packaging landscape and detailed chiplet and package co-design obstacles.
Ms. Fontanelli summed up Advanced Product packaging as incorporating various heterogeneous assimilation methods, consisting of multi-chip components, with silicon using 2.5 and 3D assimilation, fan-out wafer-level product packaging, system-in-package, chiplet-based assimilation, and/or, system dis-aggregation and re-aggregation. Simply put, “everything but the chips,” she stated.
“The most demanding IC systems today combine multiple components such as chiplets, memory and ASICs. The package poses the challenge of handling, updating & optimizing complex interconnects in a 3D space,” Ms. Fontanelli described.
Contemporary 3D chiplet design needs pass away piling and silicon-to-silicon upright interactions capacities utilizing a mix-and-match “LEGO-like” setting up. This brand-new chiplet product packaging needs brand-new devices, brand-new approaches, and brand-new circulations, she described.
One freshly readily available option is MZ Technologies’ GENIOTM, the very first incorporated IC/Packaging EDA device. GENIOTM is an advanced layout setting incorporating standard silicon, package, and PCB layout streams in one solitary circulation. It offers capacities for system design expedition, suppose evaluation, and I/O preparation & & optimization, utilizing exclusive formulas that successfully map 3D interconnects.
GENIOTM does not overlap with existing innovations, instead it fills up the voids exposed by of the significant EDA devices. Therefore, brand-new performances relate to timing/power/thermal evaluation and physical manufacturability.
Ms. Fontanelli described just how the GENIOTM alternative layout setting covers the total 3D layout environment. Its co-design system allows a cutting edge technique to incorporating with physical application devices in both IC and package layout rooms, in addition to carrying out signal, power honesty, and pre-layout thermal evaluation for physical-aware and simulation-aware system adjoin optimization.
She likewise exposed that on a real-design examination instance, GENIOTM lowered building layout time by 60X,
Concerning Monozukuri
Monozukuri’s goal is to dominate 2.5 D & & 3D layout obstacles for future generation digital items by supplying ingenious, ground-breaking EDA software application options and approaches. The modern technology redefines the co-design of heterogeneous microelectronic systems by offering an enhanced degree of automation in three-dimensional adjoin optimization.
