Saras Micro Devices (Saras), a leading provider of cutting-edge system power performance solutions with integrated packaging design, is proud to announce its participation in two major projects funded by the U.S. Department of Commerce CHIPS National Advanced Packaging Manufacturing Program (NAPMP). Each project has been awarded $100 million in government funding.
The first project, called Substrate-based Heterogeneous Integration Enabling Leadership Demonstration for the USA (SHIELD USA), is led by Arizona State University (ASU) and Deca Technologies, Inc. The second project is the Substrate and Materials Advanced Research and Technology (SMART) Packaging Program, led by Absolics, Inc. Saras will be contributing its STILEâ„¢ product technology to both projects to enhance device package integration for advanced power delivery solutions in high-performance computing (HPC) and artificial intelligence (AI) applications.
“Saras’ STILE technology enhances our substrate efforts,” said Jason Conrad, Chief Operating Officer of ASU’s Southwest Advanced Prototyping (SWAP) Hub. “It adds functionality that complements our core development goals, helping to elevate the capabilities of the advanced packaging solutions we’re developing.”
Saras has recently obtained seven foundational patents for its capacitor and STILE technologies from the United States Patent Trademark Office. This achievement demonstrates the company’s dedication to innovating critical solutions for power delivery in next-generation AI and HPC devices.
“The power delivery challenges posed by AI require innovative solutions,” stated Ron Huemoeller, CEO of Saras. “Our STILE technology addresses these challenges by enabling in-package power delivery close to the source, improving efficiency, performance, and opening up package real estate for higher levels of chiplet integration. By collaborating on the SHIELD USA and SMART projects, we’re able to contribute crucial AI power delivery elements and advance U.S. semiconductor manufacturing capabilities.”
STILE introduces a multi-domain, integrated passive module that embeds directly into the substrate core of device packages. This approach reduces the need for multiple function-specific devices, maximizes packaging real estate, and supports higher levels of chiplet integration, essential for AI workloads. The technology aligns with the goals of the NAPMP projects and will extend the advanced substrate technology solutions that the SHIELD USA project and SMART Packaging Program aim to deliver.
“This joint effort demonstrates how integrating complementary innovations can drive advancements in semiconductor packaging to meet the performance demands of AI and HPC applications,” said Craig Bishop, CTO of Deca Technologies.
The collaborations under the NAPMP advanced substrate and material projects underline the importance of innovative power delivery solutions in maintaining U.S. leadership in semiconductor technology. By developing and scaling advanced packaging processes, materials, and equipment, these initiatives aim to create a solid foundation for high-volume semiconductor packaging production in the United States, enhancing national security and economic resilience.
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