Heterogeneous integration and AI are advancing together to meet the increasing demand for computing power while reducing energy and time needed for training models. Nvidia and TSMC are developing larger, more complex packages to handle this learning process, with TSMC’s latest AI processor being a 2x reticle package and TSMC’s OIP featuring a 9x reticle package with 12 HBM4 memory modules.
By 2030, it is expected that multi-reticle packages will reach 1 trillion transistors, as discussed at the SEMI ISS event in January 2025. High-performance computing, which currently accounts for 40% of the industry’s revenue, is emphasizing packaging technology to enable placing multiple dies and memory in the same package for improved latency and reduced power consumption.
Key figures in the industry, such as Kevin Zhang from TSMC and Oreste Donzella from KLA, are leading the transition to advanced packaging and heterogeneous integration. Technology changes like panel-level processing, large interposers, and glass core substrates are enabling the development of these large multi-reticle packages.
To further scale these packages, the industry is moving towards hybrid bonding, which offers advantages such as smaller pitches for increased IO and bandwidth communication between chips. Companies are actively working on implementing hybrid bonding for high-bandwidth memory, despite challenges with die-to-wafer and wafer-to-wafer contact, cleanliness, and planarization.
Vertically integrated companies are making progress in advancing the technology for multi-reticle packages in high-performance computing. Despite differences in roadmaps, the competition and drive for innovation are pushing the industry forward.
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